This invention relates generally to the field of micro-structures, and more particularly to a method for making insulating micro-structures.
When a micro-structure such as a micro-electromechanical (MEMS) device is constructed, the most common substrate used is silicon. Silicon is a semiconductor, and MEMS devices must consider and control that property in the design and manufacture of MEMS products. As a MEMS device is fabricated, part of the silicon oxidizes to form silicon oxide (xe2x80x9cSiOxe2x80x9d), silicon dioxide (xe2x80x9cSiO2xe2x80x9d), or a similar compound of oxidized silicon (xe2x80x9cSiOxxe2x80x9d) (together, xe2x80x9coxidized siliconxe2x80x9d), all of which are insulators. When the oxidized silicon is not desired for the application, it is removed using an oxide-specific etch. For some applications, the oxidized silicon is retained for use as an insulator between metal applied on top of the device and the silicon substrate. Even so, this form of insulation is inadequate for many applications because metal-oxide-silicon interfaces are sources of parasitic capacitance that impair the performance of certain devices, such as those relying on opposing metal layers for capacitive actuation and transduction. For example, the large area provided by the structure sidewalls in U.S. Pat. No. 5,719,073 (Shaw et al.) and the metal-oxide-silicon structure directly results in a large parasitic capacitance. For many MEMS devices, the variable capacitance provided by opposing structure sidewalls can be exceeded by the parasitic capacitance to the silicon substrate. When capacitance detection is used to measure the displacement of a MEMS sensor, this large parasitic capacitance to the substrate is a source of noise.
Various techniques to reduce parasitic capacitance are disclosed in U.S. Pat. Nos. 5,426,070 and 6,239,473. These techniques vary in effectiveness, but none offers a perfect solution. The processes for forming actuators and isolation joints, and releasing them from the underlying silicon substrate, are discussed in U.S. Pat. No. 6,239,473 (Adams et al.) entitled TRENCH ISOLATION PROCESS FOR MICROELECTROMECHANICAL DEVICES; U.S. Pat. No. 5,719,073 (Shaw et al.) entitled MICROSTRUCTURES AND SINGLE-MASK, SINGLE CRYSTAL PROCESS FOR FABRICATION THEREOF; U.S. Pat. No. 5,846,849 (Shaw et al.) entitled MICROSTRUCTURE AND SINGLE MASK, SINGLE-CRYSTAL PROCESS FOR FABRICATION THEREOF; U.S. Pat. No. 6,051,866 (Shaw et al.) entitled MICROSTRUCTURES AND SINGLE MASK, SINGLE-CRYSTAL PROCESS FOR FABRICATION THEREOF; S. G. Adams, et. al., xe2x80x9cSingle-Crystal Silicon Gyroscope with Decoupled Drive and Sensexe2x80x9d, in Micromachined Devices and Components V, Patrick J. French, Eric Peeters, Editors, Proceedings of SPIE Vol. 3876, 74-83 (1999); K. A. Shaw, Z. L. Zhang, and N. C. Macdonald, xe2x80x9cSCREAM I: A single mask, single-crystal silicon process for microelectromechanical structuresxe2x80x9d, Sensors and Actuators A, vol. 40, pp. 63-70 (1994); and Z. L. Zhang, N. C. MacDonald, xe2x80x9cA rie process for submicron, silicon electromechanical structuresxe2x80x9d, J. Micromech. Microeng., v2, pp. 31-38 (1992), all of which are incorporated herein by reference in their entirety.
Briefly stated, a method of manufacturing insulating structures by etching and filling a plurality of trenches in close proximity in a silicon substrate. The trenches are configured such that, during oxidation, the silicon substrate that separated the trenches is completely oxidized and the former trenches become filled or nearly filled with oxidized silicon. Another layer of insulation, such as more oxidized silicon, silicon nitride, or some other insulating substance, is then deposited on top of the oxidized silicon to fill any remaining trenches, thus forming an insulating structure with a relatively smooth surface. When the top of this insulating structure is metallized, the structure reduces the capacitive coupling between the metal and the silicon substrate. The trenches can be arranged arbitrarily in the substrate to define patterns as desired. Part of the silicon substrate underlying the structure optionally can be removed to reduce further the capacitive coupling effect. Metal also can be applied optionally to the top and side(s) of the structure as particular applications may require.
According to an embodiment of the invention, a method of manufacturing an insulating microstructure includes the steps of (a) providing a silicon substrate; (b) etching a plurality of trenches in the silicon substrate; (c) oxidizing the plurality of trenches until the silicon between the trenches is fully oxidized; and (d) depositing an insulator to fill what remains of the trenches after the step of oxidizing.
According to an embodiment of the invention, an insulating micro-structure is formed by the steps of (a) providing a silicon substrate; (b) etching a plurality of trenches in the silicon substrate; (c) oxidizing the plurality of trenches until the silicon between the trenches is fully oxidized; and (d) depositing an insulator to fill what remains of the trenches after the step of oxidizing.
According to an embodiment of the invention, an insulating micro-structure is formed by the steps of (a) providing a silicon substrate; (b) etching a plurality of trenches in the silicon substrate; (c) oxidizing the plurality of trenches until the silicon between the trenches is fully oxidized; (d) depositing an insulator to fill what remains of the trenches after the step of oxidizing; (e) depositing a pattern of metal on a side of the structure opposite the silicon substrate; and (f) removing the silicon substrate from beneath a portion of the structure.
According to an embodiment of the invention, a method of manufacturing a hybrid silicon-insulator structure includes the steps of (a) providing a silicon substrate; (b) etching a plurality of trenches in the silicon substrate wherein the trenches are spaced sufficiently apart to prevent the silicon substrate between the trenches from being completely oxidized during the step of oxidizing; (c) oxidizing the plurality of trenches; and (d) depositing an insulator to fill what remains of the trenches after the step of oxidizing, thus forming the hybrid silicon-insulator structure.
According to an embodiment of the invention, a hybrid silicon-insulator structure is formed from the steps of providing a silicon substrate; etching a plurality of trenches in the silicon substrate wherein the trenches are spaced sufficiently apart to prevent the silicon substrate between the trenches from being completely oxidized during the step of oxidizing; and depositing an insulator to fill what remains of the trenches after the step of oxidizing, thus forming the hybrid silicon-insulator structure.
According to an embodiment of the invention, a hybrid silicon-insulator structure is formed by the steps of providing a silicon substrate; etching a plurality of trenches in the silicon substrate wherein the trenches are spaced sufficiently apart to prevent the silicon substrate between the trenches from being completely oxidized during the step of oxidizing; depositing an insulator to fill what remains of the trenches after the step of oxidizing, thus forming the hybrid silicon-insulator structure; depositing a pattern of metal on a side of the structure furthest away from the silicon substrate; and removing the silicon substrate from beneath a portion of the structure.
According to an embodiment of the invention, a hybrid silicon-insulator structure is formed by the steps of providing a silicon substrate; etching a plurality of trenches in the silicon substrate wherein the trenches are spaced sufficiently apart to prevent the silicon substrate between the trenches from being completely oxidized during the step of oxidizing; depositing an insulator to fill what remains of the trenches after the step of oxidizing, thus forming the hybrid silicon-insulator structure; depositing a pattern of metal on a side of the structure furthest away from the silicon substrate; removing the silicon substrate from beneath a portion of the structure; and adding metal to the top and side(s) of the hybrid silicon-insulator structure.